Verilog HDL: Digital Design and Modeling (英語) ハードカバー – 2007/2/20
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Emphasizing the detailed design of various Verilog projects, Verilog HDL: Digital Design and Modeling offers students a firm foundation on the subject matter. The textbook presents the complete Verilog language by describing different modeling constructs supported by Verilog and by providing numerous design examples and problems in each chapter. Examples include counters of different moduli, half adders, full adders, a carry lookahead adder, array multipliers, different types of Moore and Mealy machines, and much more. The text also contains information on synchronous and asynchronous sequential machines, including pulse-mode asynchronous sequential machines.
In addition, it provides descriptions of the design module, the test bench module, the outputs obtained from the simulator, and the waveforms obtained from the simulator illustrating the complete functional operation of the design. Where applicable, a detailed review of the topic's theory is presented together with logic design principles, including state diagrams, Karnaugh maps, equations, and the logic diagram.
Verilog HDL: Digital Design and Modeling is a comprehensive, self-contained, and inclusive textbook that carries all designs through to completion, preparing students to thoroughly understand this popular hardware description language.
Santa Clara University, California, USA
Note that if you are new to Verilog (but not to programming in general) the book is quite easy to read. Note that in order to fully grasp Verilog, in my opinion, you need to read the entire text (all 770+ pages) and work the examples. The explanation of Verilog is not condensed with follow-on project. The approach is to get you started with simple examples of what is presented in latter chapters. The various parts of Verilog are then covered in more depth. Some may not like this approach opting, instead, for a book that has complete projects on a specific kit (Xilinx Spartan 3, etc.). This is not the book for those individuals. There are plenty of books on Verilog. This book happens to fit my need to cover Verilog with, what I would describe, and "architectural twist". Mr. Cavanagh's other book complements this book.
The contents of the book are as follows:
Chapter 1 Introduction
Chapter 2 Overview
Chapter 3 Language Elements
Chapter 4 Expressions
Chapter 5 Gate-Level Modeling
Chapter 6 User-Defined Primitives
Chapter 7 Dataflow Modeling
Chapter 8 Behavioral Modeling
Chapter 9 Structural Modeling
Chapter 10 Tasks and Functions
Chapter 11 Additional Design Examples
Appendix A Event Queue
Appendix B Verilog Project Procedure
Appendix C Answers to Select Problems
Most important: There is NO discussion of synthesis at all. None. You will not learn from this book which Verilog constructs are synthesizable, or how they are synthesized. You may very well get the impression from this book that everything you do in Verilog can be made into hardware, because the book never says otherwise. In fact, take a hint from the subtitle of this book: it contains the word "modeling" and does not contain the word "synthesis". You will not learn, for example, that the reg type does not necessarily synthesize into a register - which is key knowledge if you want to use combinatorial logic in a always block and are worried that needing to use a reg type means it will be clocked. I had to look to the web to discover this.
Next: Book is copyrighted 2007 but as far as it is concerned Verilog-2001 doesn't exist. Verilog-2001 has a lot of nice syntax and feature improvements. No reason to be limited to earlier Verilog syntax/semantics any more, but you won't learn anything about it here. (It would have made the examples shorter too.)
Finally: There is no discussion of the Verilog "gotchas", as described with terrific explanations in the papers by Sutherland, Mills, and Spear. (Google for "Standard Gotchas Verilog" and "More Gotchas Verilog".) It would really be nice in this textbook to have coverage of the several of these common issues, especially sign-extension (or non-extension) when connecting or operating with nets/regs of different sizes, and also the issues of case fullness or parallelness. (The papers came out contemporary with the book, I'm not suggesting that the author should have copied the papers here, but surely he knew of these issues independently and could have covered them.)
Anyway - books in the HDL field (or maybe just Verilog) seem to be poor in general, for a variety of reasons. This one isn't badly written, it just doesn't cover some important stuff. And in particular, it doesn't cover synthesis (esp. in the FPGA context), which is what I was looking for.
Oh, one more thing. 70 pages are devoted to "gate level modeling". Wow. There must be some reason to have that stuff in the language; it must be useful to someone. But I sure don't know why anyone needs to use it, especially not the beginning students that this book is aimed at. And the same for K-maps. K-maps have a long history and they're very useful if you're optimizing gates by hand. But now we have logic compilers (i.e., Verilog/VHDL compilers) and I can't see any reason why you can't just go from state machine diagrams to synthesizable code without ever touching a K-map. Looking at the diagrams in this book you'd think they were crucial. Very odd.
It is true that there is much material in the book and the author is very rigorous about providing test code for each example, but it is a book for people who need cook books. The book is long and repetitious. About one-third of the way through, I lost interest, but did manage to plod my way through most of the remaining sections.
There is not an organized tutorial explaining the syntax and there is no reference section. Instead material is spread throughout the book. I believe there is fundamental information missing such as how does the compiler interpret the language; e.g., how do the statements relate to flip-flops in hardware. You almost have to know other languages to understand.