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Computer Arithmetic and Verilog HDL Fundamentals
 
 

Computer Arithmetic and Verilog HDL Fundamentals [ハードカバー]

Joseph Cavanagh

参考価格: ¥ 12,623
価格: ¥ 12,487 通常配送無料 詳細
OFF: ¥ 136 (1%)
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2012/5/31 木曜日 にお届けします! 「お急ぎ便」オプション(有料)を選択して注文を確定された関東エリアへの配達のご注文が対象です。詳しくはこちら

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内容説明

Verilog Hardware Description Language (HDL) is the state-of-the-art method for designing digital and computer systems. Ideally suited to describe both combinational and clocked sequential arithmetic circuits, Verilog facilitates a clear relationship between the language syntax and the physical hardware. It provides a very easy-to-learn and practical means to model a digital system at many levels of abstraction.

Computer Arithmetic and Verilog HDL Fundamentals details the steps needed to master computer arithmetic for fixed-point, decimal, and floating-point number representations for all primary operations. Silvaco International’s SILOS, the Verilog simulator used in these pages, is simple to understand, yet powerful enough for any application. It encourages users to quickly prototype and de-bug any logic function and enables single-stepping through the Verilog source code. It also presents drag-and-drop abilities.

Introducing the three main modeling methodsdataflow, behavioral, and structuralthis self-contained tutorial

  • Covers the number systems of different radices, such as octal, decimal, hexadecimal, and binary-coded variations
  • Reviews logic design fundamentals, including Boolean algebra and minimization techniques for switching functions
  • Presents basic methods for fixed-point addition, subtraction, multiplication, and division, including the use of decimals in all four operations
  • Addresses floating-point addition and subtraction with several numerical examples and flowcharts that graphically illustrate steps required for true addition and subtraction for floating-point operands
  • Demonstrates floating-point division, including the generation of a zero-biased exponent

Designed for electrical and computer engineers and computer scientists, this book leaves nothing unfinished, carrying design examples through to completion. The goal is practical proficiency. To this end, each chapter includes problems of varying complexity to be designed by the reader.

著者について

Joseph Cavanagh is an adjunct professor in the computer engineering department at Santa Clara University in California.


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Exceptional book on computer arithmetic and Verilog 2011/8/11
By P. Karnes - (Amazon.com)
形式:ハードカバー
I am a hardware engineer designing an execution unit and find the book to be extremely well-written, providing a comprehensive coverage of both computer arithmetic and Verilog HDL. The theory and architecture for all designs are covered prior to implementing the designs in Verilog.
Before proceeding with this review, I would like to comment on the one-star reviews that were given for this book. The criticisms provided by these reviewers are completely unfounded and obviously inaccurate. This is an excellent, well-written book and all of the material is explained in detail. It is one of the best books available on the topic. The Verilog software is the latest version produced by Silvaco International called the SILOS Simulation Environment and is definitely current. Also, it is obviously extremely unlikely that one of the reviewers contacted all of the other buyers and were told that they bought only this book. These reviewers obviously intended to degrade this book for their own personal agenda. They obviously have not read the book. I am certain that an objective reviewer will agree with the preceding comments.
The book provides a thorough presentation and Verilog designs of fixed-point arithmetic, including both low-speed serial addition/subtraction and high-speed carry lookahead addition/subtraction for the fixed-point number representation. The same is true for fixed-point multiplication, which covers a sequential add-shift multiplier, a Booth algorithm multiplier, and a high-speed array multiplier. A high-speed memory-based multiplier is also presented. Fixed-point division is presented in detail for SRT division, multiplicative division, and a high-speed array divider.
Decimal addition details a design using multiplexers that provide a high-speed operation. There is also a memory-based decimal adder. Decimal subtraction provides the theory and designs for different techniques. Decimal multiplication provides the architecture and Verilog designs using behavioral modeling and structural modeling. There is also a high-speed memory-based multiplier. The book presents the table lookup division technique plus the theory and Verilog designs of the restoring division method.
The chapters on floating-point cover in detail the floating-point format, biased exponents, overflow, underflow, and the theory for addition, subtraction, multiplication, and division. Flowcharts are provided that depict the algorithms utilized for the four arithmetic operations. A Verilog example illustrates using behavioral modeling for floating-point addition. Different Verilog versions are given for floating-point subtraction. Double and zero biases are covered for multiplication and division, respectively, together with different Verilog versions for multiplication.
There is a chapter on additional floating-point topics. These topics include the rounding techniques of truncation, adder-based, and von Neumann rounding. A section on guard bits is also included. Verilog designs are presented for the various rounding methods.
The book provides additional topics on computer arithmetic. These include the theory, architecture, and Verilog designs of residue checking using dataflow modeling and structural modeling. A section on parity checking is also included, complete with theory and Verilog design. Parity prediction, which is a form of checksum error detection, is presented, including the theory, architecture, and Verilog design. Various other logic designs are also included in this chapter.
The book also provides Appendices on the Verilog designs of various combinational logic functions, the event queue used in Verilog, and answers to select problems, which are a tremendous help to students.
The author includes the design module, the test bench module, the outputs, and the waveforms for the arithmetic designs, all of which most other books do not include. The Verilog code is well formatted and easy to read. I highly recommend this book.
Make your day 2012/3/30
By H. Callahan - (Amazon.com)
形式:ハードカバー
If you feel lucky, then go ahead and make your day by reading this popular book on computer arithmetic enhanced with Verilog HDL. The book is extremely grammatically polished and comprehensive. The arithmetic circuits for fixed-point, decimal, and floating-point are presented in detail for addition, subtraction, multiplication, and division. The circuits are designed using the popular hardware description language of Verilog HDL from Silvaco International. The design constructs include built-in primitives, user-defined primitives, dataflow modeling, behavioral modeling, and structural modeling. I have found the answers to certain problems in the Appendix to be especially helpful. As with all of his books, the author is well qualified as a writer on this topic. Like other reviewers, I recommend all of the author's books.
Excellent book on computer arithmetic 2012/2/9
By R. Martin - (Amazon.com)
形式:ハードカバー
Well-written, this book presents computer arithmetic as designed using Verilog HDL. The fixed-point, decimal, and floating-point number representations are covered in detail for the four arithmetic operations. Different design methodologies are given for each arithmetic operation. The different Verilog modeling constructs are presented in detail. These include: built-in primitives, user-defined primitives, dataflow modeling, behavioral modeling, and structural modeling. There is also an appendix that presents answers to select problems. This author is well versed and highly qualified both as an engineer and as a writer. I highly recommend all of the author's books.

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